AutoStream global are pleased to be working with an innovative hardware designer, with offices and factories across the globe. This role is in Zurich.
We are supporting their search for a SoC Mixed Signal Verification Engineer
- The owner of the complete SoC verification activity as such you will:
- Develop Test Plan (coverage driven & constraint random verification)
- Create chip-level and/or IP level automated testbenches with embedded checkers
- Develop and use assertion-based verification and formal analysis methods
- Setup and debug regressions for RTL, Gate Level Netlist, Power Aware simulations
- Ensure structured regression reporting to ease designers debugging
- Track (through bug tracking system) and follow-up on failing cases with each IP owner
- Responsible to extend verification boundaries
- Develop analog models (Mix and match wreal/transistors models at SoC level)
- Combine measurements from different regression environments (IP/SoC/Lab) into dashboard.
- Rerun verification tests in lab (Pyvisa) or port lab tests into simulations
- Run UVM testbench in analog environment
- Support post-silicon activities.
- Provide bring-up validation pattern to lab Engineers
- Support debugging silicon failures through corelated simulations
- Document and present verification strategy within Mix-Signal environment.
- Documentation & integration guidelines to maximize reuse across multi-projects
- Collaborate across Company's multi-sites/multi-country activities to support verification deployment
- Must be able to leverage your expertise to provide team technical training
- A Ph.D. degree with 3+ years of experience or a M.S in Electrical Engineering with 5+ years of experience in Soc Verification with proven track record of putting designs into production
- Good experience of SoC verification within a mix-signal environment (wreal, SV-RNM, Verilog AMS)
- Strong expertise in Universal Verification Methodology
- Proficient in SystemVerilog, SystemC or E Language
- Notions of signal processing (FFT, filtering, noise) and signal processing tools (Python (pylab) / Matlab)
- Familiar with VHDL / Verilog development and experience in analog circuit design is a plus.
- Familiar with Cadence design & simulation suite and good scripting capabilities (Bash/TCL/Python/Perl)
- Prior exposure to Linux and open source projects to gain embedded system understanding (Arduino, raspberry pi, QEMU) is a plus.