Senior Digital Design & Verification Engineer

TechStream Global are delighted to be working with a global semiconductor business for a Senior Digital Design & Verification Engineer

The role has responsibilities to develop the best product architecture targeting Edge-IoT applications (sensor fusion, keyword spotting, object detection, image classification, etc.), machine learning (ML) and artificial intelligence (IA).

The position is located within the Digital Design Processing & ASIC division. You responsible for all digital developments for IPs and ASICs, from architecture definition to front-end / middle-end implementation.

You will help make verification decisions to meet performance and power goals for products such as the CHAMELEON microcontroller, PANTHER DSP, and RAPTOR neural processing unit.

Responsibilities

• Design: - Work closely with the architect to develop the product design according to specifications. - Develop the product taking into account the functional and power aspects. Compromise between requirements (technical and non-technical) and development costs. Development of the RTL code related to the functional design Development of the UPF code for a power-sensitive design Lint Checks Clock Domain Crossing (CDC) checks - Specify the time constraints (SDC) of the product to allow the execution of the middle-end activities (summary, equivalence checks, timing analysis).
• Verification: - Responsible for the "functional and power-aware verification" of the product. Work closely with the architect and designers to define the objectives and the verification strategy of the product according to the specification. Definition of the verification plan (coverage-driven methodology) Development and debugging of an advanced verification test bench based on uVM Development of the coverage strategy and tests for parameterized IPs (SystemVerilog language) Functional, performance and power verification RTL debugging, non-regression, audit close - Provide support to design team members during project execution.
• Methodology: - Contribute to the continuous improvement and maintenance of the methodology and the flow of verification. - Provide training and support to other team members for verification activities
• Project execution: Provide internal support and advice for design and verification activities. Participate in the assessment, implementation and execution of projects in close collaboration with project managers and other team members.

Knowledge and know-how

• 5 years of experience in a similar position.
• Design and verification methodologies
• RTL coding (VHDL, Verilog, SystemVerilog), lint, CDC checks
• Knowledge of AMBA and AMBA VIPs protocols
• Knowledge of ARM and / or RISCV integration
• UPF standards (UPF2.0 / 2.1) and static control methodologies for low power design
• uVm based testbench infrastructure
• Knowledge of uVM verification methodology
• Stream of low-power SoC architecture, design and implementation for extremely low power consumption
• Cadence, Mentor and Synopsys EDA tools covering all stages of the flow
• Script: Tcl, Shell, Perl, Python
• Linux / Windows working environment
• Prior exposure to QuestaFormal is advantageous