Digital Mixed Signal Verification Engineer
- Location England
- Job-type Full time
- Salary Negotiable
- Sector SemiConTech
- Reference PR/007532_1626251499
- Start date ASAP
l-Mixed-Signal Verification Engineer (f/m/d)
Neuchatel, Switzerland
AutoStream Global are delighted to be supporting a global semiconductor business to recruit a Digital-Mixed-Signal Verification engineer who will enable bug-free first silicon for the digital-/analog and mixed-signal designs.
Responsibilities
Pre-silicon verification including:
- Developing and verifying analog behavioural models (e.g. LNA, PLL, ADC, DAC, Mixer,..)
- In System Verilog at different abstraction levels, matching the schematic specifications till the pre-silicon sub-/system verification with main respect to Analog/Mixed-Signal macros in close collaboration with multiple disciplines.
- As a verification engineer you have ownership of functional analog macro sign-off which includes the communication of status and results into the existing verification management framework.
Key Qualifications
Experience in Analog design
Experience with digital simulation tools (Cadence NCsim, Synopsis VCS, Mentor Modelsim and/or Mixed Signal simulation tools like Cadence AMS-Designer, Synopsis VCSXA, Mentor Questa)
Ability to read and understand schematics to define and implement functional behavioural models
Ability to think on different abstraction levels from very detailed component to system-level
3+ years of experience in hardware description languages like System Verilog, VHDL, Verilog
Outstanding sense and drive for quality of deliverables
Verification mindset
Reliable, ability to work independently as well as in a team environment
Good interpersonal and communication skills
System know-how in the cellular RF transceiver domain is a plus
C/C++ programming language for testcase development is a plus
Description
Developing analog behavioural models in System Verilog
Running model versus schematic correlation simulations to guarantee the matching to the schematic specifications
Defining/verifying verification requirements
Coding of test scenarios and assertions
Doing sub-/system verification with existing UVM top level test benches
Interacting with analog and digital design engineers, firmware engineers, RF layout engineers.
Education & Experience
Degree in Computer Science, Computer Engineering, Mechatronics, Electronics or equivalent