AutoStream are delighted to be working with a 5-year-old fast growing fabless semiconductor startup established in Grenoble, France. Their product is the world's first IoT Application Processor armed with 8+1 RISC-V based cores and a high performance HW convolution engine. It is a simple yet very sophisticated unique processor architecture, which delivers an energy efficiency that is 20x better than the state-of-the-art, opening a large range of battery powered applications.
Examples of applications are people counting, keyword spotting, combined with beamforming, object recognition, face detection and vibration analysis. GAP8 is especially effective on machine learning inference algorithms (CNN, SVM, Bayesian, Boosting, Cepstral analysis). Yet, GAP8 is by and large programmed just like a regular MCU. Our client´s technology is very much ahead of the state-of-art, and their chip is just about to prove its revolutionary potential on a wide open global market.
As a growing and highly multicultural team with sharp personalities, our client is very proud of its specific collaborative management style.
As a member of the circuit design team, you will actively contribute to the verification of their next generations of chips:
- Building up of verification plan in relation with SoC architects and designers: features to be tested, test strategy, target coverage, description of tests and conformity matrix;
- Setup of testbenches (SystemVerilog/UVM) at IP, subsystem and/or top chip levels;
- Interfacing with software team for specific embedded SW developments required for test;
- Implementation and execution of planned tests, analysis of results and report of encountered bugs;
- Continuous improvement of verification environments: packaging of in-house verification IPs for reuse on different testbenches, automation of tests and non-regression procedures, etc.;
- Interfacing with the design team for analysis and fixing of bugs; ● Associated documentation.
- Command of ASIC verification methods and techniques, preferably using UVM;
- Skills in corner case-driven, coverage-driven and possibly formal verification;
- RTL simulation and debug using EDA tools (e.g. NCSim, Xcelium);
- Knowledge of usual EDA scripting languages (TCL, Bash, Makefile);
- C programming in embedded environments;
- Familiarity with versioning/revision control systems.
- Liking for debug and problem solving;
- Good level of spoken and written English, to be used daily to communicate with colleagues and international partners;
- Organizational skills;
- Strong team spirit and communication abilities;
- Ability to work autonomously and proactively on assigned tasks.
- Command of UVM-based verification and setup of complex UVM testbenches;
- Skills in power and performance verification;
- Knowledge of RTL static checks (lint, CDC, power checks…) is a plus;
- Git proficiency;
- Knowledge of the overall ASIC design flow, at least at a high level;
- Master´s Degree or plus with a specialization in microelectronics;
- A first experience in RTL verification is mandatory, preferably using UVM methodology;
- Experience in other parts of ASIC design flow is a plus: design, RTL checks, synthesis, equivalence checking, etc. Employment type: Full time (CDI) Location: Grenoble, France (Alsace-Lorraine near train/tram) Competitive compensation and stock option plan